FPGA Design Utilization
The high-speed digital processing parts of the Panoradio are implemented on the FPGA. The Zynq 7020 features a 7-series FPGA from Xilinx, which belongs to the mid-sized Zynq SoCs with in total 53.200 Look-Up tables and 106.400 flip-flops, 560 KB SRAM and 220 DSP slices.
The FPGA for the Panoradio design is less than 50% occupied. This quite low utilization would allow for even more complex DSP. However, I observed, that the Zedboard does not cope very well with high FPGA utilization in certain applications. Then it seems to have problems to deliver enough supply to the Zynq and operation becomes instable (also discussed in the official forum).
The main contributor to the radio’s complexity is the Waterfall DDC, because it operates for high sample frequencies and thus requires high parallelism. The second main contributor to the overall complexity is the interconnect between processor and FPGA, followed by the Audio demodulation and postprocessing.
The floorplan shows the placement of the different SDR parts on the Zynq chip.
FPGA Floorplan for high-speed SDR processing