DDC for Zoomable FFT

DDC for Zoomable FFT

Every SDR requires some kind of downconversion to translate signals of high frequencies to lower frequencies for demodulation or spectrum analysis. In SDRs, this is accomplished by digital down conversion (DDC). A DDC consists of an arrangement of a local oscillator, mixers, FIR and CIC filters as well as decimation stages, that determine the reception frequency, bandwidth and final sampling rate. The Panoradio uses a DDC for the zoomable FFT waterfall displays (and two more for audio reception).

The Panoradio features three waterfall displays, which can independently monitor very different portions of the whole spectrum. The waterfall displays can be zoomed in from full span (0-100 MHz) to a spectrum portion of 6.1 kHz with a resolution of down to 7 Hz. This task is accomplished by the implementation of a flexible zoom FFT with flexible bandwidth. It is a digital down coverter (DDC), that down converts and filters the selected portion of the spectrum followed by an FFT. For this purpose, two challenges have to be solved: How to implement the zoom function efficiently and how to implement three DDCs (one for every waterfall) efficiently?

waterfall zoom

Zoom function for the waterfall, here from full span to digital signals in the 20 m amateur band

Implementation of Flexible Zoom FFT

The DDC for the flexible zoom FFT is shown in the figure below. It follows the typical design of a DDC with a digital local oscillator (LO), a complex mixing stage with two multipliers and CIC and FIR filters in the I and Q path. The filters reduce the bandwidth to the desired span of the current waterfall setting. Finally, the IQ samples are stored in a memory and sent to the processor for FFT.


Schematics for the zoomable FFT

DDC for zoomable FFT spectrum display

Local Oscillator: The implemented LO generates sine and cosine waveforms using direct digital synthesis (DDS). In DDS a sine is basically generated using a large look-up table. It stores samples of a sine waveform, which is then sampled and interpolated at the desired frequency. A second table or a second address pointer generates the corresponding cosine. DDS LOs can achieve high accuracy and agility. For FPGA implementation I used the predefined Xilinx DDS IP core.

CIC and FIR Filtering: CIC filters are low-complexity circuits that combine filtering with decimation. Decimation reduces the sampling rate from 250 Msps to a fraction determined by the decimation factor between 4 and 4096 in order to relax the computational load for the FPGA in the subsequent stages. Since the Xilinx CIC design supports only low clock frequencies for large decimation values, the actually implemented 4-stage CIC filter consists of a shiftable fixed rate (64) CIC filter plus an additional one with flexible decimation. The following sharp FIR filters with 140 coefficients determine the final bandwidth and an additional decimation by a factor 8 sets the final sampling rate. The filter design has been done with Matlab’s “Filter Design & Analysis Tool”. The calculated filter parameters and coefficients were imported into the Xilinx IP cores for CIC and FIR filters in Vivado.

Zoom Functionality: The required bandwidth of the DDC needs to be very flexible between 100 MHz and 6 kHz to implement the waterfall zoom function. For the cases of 100 MHz (1x zoom) and 50 MHz (2x zoom) bandwidth, the input samples are directly routed to the memory for a real FFT. For higher zoom levels, i.e. > x4 (span <25 MHz), the signal passes through the DDC. The flexibility in output bandwidths from 25 MHz (x4 zoom) to 6.1 kHz (x16384 zoom) is achieved by a programmable CIC decimation rate of 4 to 4096 (x16 and higher) or bypassing the CIC filters (x4 and x8 zoom). By changing the CIC decimation rate by a factor of 2, the output bandwidth also changes by a factor of 2. The FIR filter remains fixed.

Frequency responses of the CIC + FIR for different zoom levels

CIC + FIR for different zoom levels from x16 to x16384 achieved by changing the decimation in the CIC from 4 to 4096

Performance: The DDC is designed for excellent performance. The DDS provides LO signals with 21 bit each and 110 dB SFDR. The stop-band attenuation of CIC and FIR filters is typically greater than 105 dB, see figure above. The 140 coefficients for FIR filtering have a large bit width of 24 bit, such that the influence of coefficient quantization is negligible. For the overall DDC even worst case, i.e. full scale, out-of-band signals appear only with very small amplitude with less than 105 dBFS. In more realistic cases the DDC will not introduce any spurious signals. The bit width of I and Q is large enough to keep the influence of quantization errors very low (the introduced quantization noise is less than few 0.1 dBs). Note, that the bit width of I and Q channels increase with decreasing bandwidth because noise power reduces and therefore SNR increases.

One DDC – Three Waterfall

Basically, for the three waterfall displays, three DDCs would be required. However, it is more efficient to share one single DDC between the three waterfalls. Then the DDC quickly switches continuously between the parameters of the different waterfall displays, captures data and calculates an FFT before switching to the next. The parameters, that need to be switched, are the center frequencies and CIC decimation rate. The local oscillator frequency quickly changes to potentially completely different values. This is possible since the DDS is very agile and can be changed instantaneously. The filters however require some time to recover from transients, which is a potential problem especially for high decimation values. However, worst case simulations of transient behaviour showed, that the system recovers very quickly and this is not an issue if the switching time stays above several 10 ms.

FFT Oversampling

For calculating the FFT to display the spectrum in the waterfall, the DDC captures 8192 I/Q samples in a memory (for 100 and 50 MHz bandwidth: 4096 samples). Then the samples are weighted with a Hann window to reduce FFT leakage. A complex FFT is carried out resulting in 8192 frequency bins. Since the monitor resolution is too low to display a 8192 point spectrum, the oversampled spectrum is scaled down to 1024 points by summing eight neighbouring bins. This approach has another big advantage: I largely increases the resolution and sensitivity for detecting signals that are masked by the “leakage bell” of strong signals, see figure below. Improvements of some ten dBs occur in the vicinity of strong signals.

Optionally, the Panoradio can do several data captures and FFT operations consecutively in order to display the average spectrum. This does not reduce the noise floor, but reduces “fluctuations” in the spectrum plot.

Simulation of the downscaled FFT (noise floor does not match the true ADC)

Simulation of the oversampled and downscaled FFT (noise floor does not match the true ADC)



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