The SDR implementation for signal processing includes down conversion, interfaces, control and demodulation on the Xilinx Zynq device. High-speed data is handled in the FPGA part (PL) of the Zynq, whereas low data rate tasks are handled by the processor (PS).
High-speed processing in the FPGA consists of an ADC data interface followed by digital down converters (DDCs) for the waterfall displays and the audio receivers. Also sound and HDMI interfaces are implemented on the FPGA. FPGA implementation has been done with Xilinx Vivado using some Xilinx IP predefined cores (e.g. for filters) and many customly designed VHDL blocks.
Slow-speed processing in the processor includes runnning a GUI to control the radio, displaying received signals and executing demodulation software. The demodulation software uses audio signals from the audio receivers as input to receive e.g. digi modes like RTTY, PSK31 and many more.
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